Hi John, John Youn <johnyoun@xxxxxxxxxxxx> writes: > The following patch series addresses the core reset and force mode > delay problems we have been seeing on dwc2 for some platforms. > > I think I have identified the source of the inconsistencies between > platforms and this series attempts to address them. > > Basically everything stems from the IDDIG debounce filter delay, which > is a function of the PHY clock speed and can range from 5-50 ms if > enabled. This delay must be taken into account on core reset and force > modes. A full explanation is provided in the patch commit log and code > comments. > > The first two patches are prerequisites to the force mode fixes, > including one patch that was sent separately by Przemek Rudy. I have > resubmitted it with this series for convenience. > > Please help by reviewing and testing on your platforms. > > Patches were tested on: > * Synopsys HAPS platform IP 3.20a OTG, dr_mode=OTG,HOST,PERIPHERAL I'll drop this from my queue. Once someone tests, I'm hoping you can re-send without 'RFT' on subject line. best -- balbi
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