Hello,
On 2015-10-08 11:35, Javier Martinez Canillas wrote:
Hello,
On 10/08/2015 08:23 AM, Marek Szyprowski wrote:
Hello,
On 2015-10-08 08:02, Krzysztof Kozlowski wrote:
On 07.10.2015 23:26, Marek Szyprowski wrote:
Hello,
On 2015-10-07 02:30, Krzysztof Kozlowski wrote:
Introduction
============
This patchset tries to fix probing of usb3503 on Arndale board
if the Samsung PHY driver is probed later (or built as a module).
*The patchset was not tested on Arndale board.*
I don't have that board. Please test it and say if the usb3503
deferred probe
works fine and the issue is solved.
The patchset was tested on Odroid U3 board (which is different!)
in a simulated environment. It is not sufficient testing.
Difference
==========
The usb3503 device driver can be used as a I2C device (on Odroid U3)
or as a platform device connected through phy (on Arndale). In the second
case the necessary phy reference has to be obtained and enabled.
For some details please look also at thread [0][1].
[0]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348524.html
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348875.html
I'm not sure that this is the correct approach. usb3503 chip is simply
connected
to Exynos USB2 phy, so it visible on the USB bus. The real driver that
controls USB2
PHY is Exynos EHCI driver and USB3503 should not mess around it.
The ehci node (usb@12110000) has one port configured and it takes one
PHY reference (phy of id 1 - USB host). I can't see driver taking
reference to HSIC0 or HSIC1 phys... Since I cannot diagnose the error I
don't know what is really expected here.
It looks that EHCI in Exynos 5250 and 5420 still use old phy bindings. For
the reference, see Exynos4 dts and exynos4412-odroidu3.dts to check how to enable
more than one USB port (Odroid U3 has both HSIC ports enabled).
In my opinion all that is needed in case of Arndale board is forcing
reset of
usb3503 chip after successful EHCI and USB2 PHY initialization (for some
reason
initialization of usb3503 chip must be done after usb host initialization).
However I have no idea which driver should trigger this reset. Right now
I didn't
find any good solution for additional control for devices which are on
autoprobed
bus like usb.
The reset is done at the end of usb3503's probe. The question "why
usb3503 has to be initialized after EHCI and USB PHY" is still valid...
I remember that I saw some code to reset HSIC device after phy power on in case
of HSIC-connected modem chip, so maybe this is somehow common for HSIC chips
(which are some special case of 'embedded usb').
I also don't have an Arndale board and haven't followed the thread to closely
but I just wanted to mention that the ChromiumOS 3.8 tree has a workaround to
reset the HSIC phys:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/81685c447954a29d1098268776582457258dd98f%5E%21/
and later a "supports-hsicphy-reset" DT property was added to force the reset
per board instead of unconditionally:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/a4d1c1a223ffa1ed38a4257d0378ca70c6667be0%5E%21/
I didn't check this approach, but for me it looks that the problem is caused
by the lack of resetting the chip connected to hsic phy not the lack of
resetting the phy itself. However this is pure speculation and one should
check it with the real hardware.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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