On 09/22/2015 04:16 PM, Mian Yousaf Kaukab wrote:
From: Gregory Herrero <gregory.herrero@xxxxxxxxx> Some high speed mass storage devices fail to enumerate with following error: Cannot enable port %i. Maybe the USB cable is bad? This happens only when the device is plugged while the controller is in hibernation state. After exiting hibernation, the controller detects the device as a low speed device and fail to enumerate it. Problem occurs only if HPRT0.PWR bit is programmed in a too short delay after exiting hibernation. Dumping hprt register in _dwc2_hcd_resume() directly after dwc2_exit_hibernation() shows that HPRT0.LNSTS (D+/D- level) becomes valid approximately 2ms after exiting hibernation.
Since dwc2_exit_hibernation() is called from atomic context, move the delay out of this function.
Hm, I don't see Gregory moving anything in this patch...
Delay value is experimental and not mentioned in Synopsys documentation. To be on the safe side 3ms delay is used. Signed-off-by: Gregory Herrero <gregory.herrero@xxxxxxxxx> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@xxxxxxxxx> Tested-by: Robert Baldyga <r.baldyga@xxxxxxxxxxx> --- drivers/usb/dwc2/hcd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index de9d2e2..65044da 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -2472,6 +2472,9 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) spin_unlock_irqrestore(&hsotg->lock, flags); dwc2_port_resume(hsotg); } else { + /* Wait for controller to correctly update D+/D- level */ + usleep_range(3000, 5000); + /* * Clear Port Enable and Port Status changes. * Enable Port Power. @@ -2479,7 +2482,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | HPRT0_ENACHG, hsotg->regs + HPRT0); /* Wait for controller to detect Port Connect */ - mdelay(5); + usleep_range(5000, 7000); } return ret;
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