On 2 June 2015 at 21:35, Hauke Mehrtens <hauke@xxxxxxxxxx> wrote:
> @@ -159,6 +160,55 @@ static void bcma_hcd_init_chip(struct bcma_device *dev)
> }
> }
>
> +static void bcma_hcd_init_chip_arm(struct bcma_device *dev)
> +{
> + struct bcma_device *arm_core;
> + void __iomem *dmu;
> + u32 val;
> +
> + bcma_core_enable(dev, 0);
> +
> + usleep_range(1000, 2000);
> +
> + /* Set packet buffer OUT threshold */
> + val = bcma_read32(dev, 0x94);
> + val &= 0xffff;
> + val |= 0x80 << 16;
> + bcma_write32(dev, 0x94, val);
> +
> + /* Enable break memory transfer */
> + val = bcma_read32(dev, 0x9c);
> + val |= 1;
> + bcma_write32(dev, 0x9c, val);
> +
> + if (dev->bus->chipinfo.pkg != BCMA_PKG_ID_BCM4707 &&
> + dev->bus->chipinfo.pkg != BCMA_PKG_ID_BCM4708)
> + return;
> +
> + arm_core = bcma_find_core(dev->bus, BCMA_CORE_ARMCA9);
> + if (!arm_core) {
> + dev_err(&dev->dev, "can not find ARM Cortex A9 ihost core\n");
> + return;
> + }
> +
> + dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
> + if (!dmu) {
> + dev_err(&dev->dev, "can not map ARM Cortex A9 ihost core\n");
> + return;
> + }
> +
> + /* Unlock DMU PLL settings */
> + iowrite32(0x0000ea68, dmu + 0x180);
> +
> + /* Write USB 2.0 PLL control setting */
> + iowrite32(0x00dd10c3, dmu + 0x164);
> +
> + /* Lock DMU PLL settings */
> + iowrite32(0x00000000, dmu + 0x180);
> +
> + iounmap(dmu);
> +}
I started comparing above changes to Broadcom's reference code and I
see some potential problems.
1) You check package only
Broadcom keeps developing new SoCs so it may make sense to check both:
id and pkg. I can imagine Broadcom re-using BCMA_CORE_NS_USB20 on some
other SoC requiring different programming.
So I guess you could check for BCMA_CHIP_ID_BCM4707 ||
BCMA_CHIP_ID_BCM53018. just to be safe.
2) Init order
I believe you should init PHY first (3 iowrite32 ops), then wait for
it to setup itself with (usleep_range) and then finally init
controller (bcma_[read|write]).
3) Controller init
It should be done on every package, not just BCM4707 and BCM4708.
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