Re: Errata for Freescale root-hub TT?

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On Mon, Mar 23, 2015 at 10:11:04AM -0400, Alan Stern wrote:
> On Mon, 23 Mar 2015, Peter Chen wrote:
> 
> > For going on debugging this problem, we need
> 
> I will have the hardware only for one more day, so I may not be able to
> get all the information you want.
> 
> > - Your bus analyzer file, I think there should be no enough IN/OUT
> > tokens within one frame, does the remaining time to frame boundaries
> > is enough? 
> 
> Here's an example: There are four OUT transfers near the start of the 
> frame, and they take about 300 us.  The remaining 700 us in the frame 
> are completely idle, even though they should contain four IN transfers.

How do you know the frame has filled already at that time? The software
makes sure it fills frame in time before next time frame?

-- 

Best Regards,
Peter Chen
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