Hello. On 12/04/2014 08:35 PM, David Laight wrote:
The TX-interrupt fires (sometimes) too early and therefore we have the early_tx timer to check periodically if the transfer is done. Initially I started I started with a 150us delay which seemed to work well. This value was reduced further, because depending on the usecase a smaller poll interval was desired. Instead of tunning the number further I hereby try to get rid of the timer and instead use the TX-FIFO-empty interrupt. I've been playing with it for a while and tried various things. Here is a small summary:
- Enable TX-empty interrupt "late" The TX-empty interrupt would be enabled after "DMA IRQ" if the FIFO is still full. This seems to work in generall but after removing the debug code the TX-empty interrupt isn't generated.
- Use one of the two interrups In general, the TX-empty interrupt comes after the DMA-interrupt. But I've also seen it the other way around. So it not an option.
...
What happens if you don't even enable the 'DMA' interrupt?
If everything is actually working you won't receive a 'TX-Empty' interrupt until after the dma controller has finished the transfer.
You first need to enable that interrupt -- it's usually suppressed by using TX DMA mode 1, else it would be generated on each packet. The only place to do this is the TX DMA IRQ handler.
[...]
If someone has written a DMA interface that requires you take an 'end of transfer' interrupt, then you need to fix the DMA interface!
Basically every MUSB DMA interface is guilty of that. :-)
David
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