Re: [PATCH] usb: phy: mxs: change test clock gating on connection/disconnection

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Hi Felipe,On 05.11.2014 21:00, Felipe Balbi wrote:
> On Wed, Nov 05, 2014 at 08:52:25PM +0200, Vladimir Zapolskiy wrote:
>> On some boards powered by iMX6Q rev1.0 I get non-working USB Host 1
>> (connected to a hub, no other devices are connected to this hub) and
>> repeating resets from the chipidea host driver (with ported pm support
>> from Freescale):
>>
>>   ....
>>   [   25.481714] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
>>   [   27.491716] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
>>   [   29.501721] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
>>   ....
>>
>> As for me it seems that usb phy test clock gating may be done
>> incorrectly, on disconnection it is running, and on connection it is
>> gated, but may be it is the intention, unfortunately iMX6Q RM is not
>> a satisfactory source of information on the topic.
>>
>> Either complete disabling of loopback for the host or inverting test
>> clock gating solves my problem, this change proposes to invert test
>> clock gating setting.
>>
>> Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@xxxxxxxxxx>
>> Cc: Peter Chen <peter.chen@xxxxxxxxxxxxx>
> 
> Make sure to Cc the maintainer of the framework, that'll help make sure
> your patch is not lost.
> 

thank you for reminder, frankly speaking I should tag the change as RFC,
please do not include it for merging before Peter's review, I planned to
let you know after it happens.

It is a fix for me, but I don't know, if it is a completely correct fix
or if it has drawbacks (none are known to me so far, moreover in vanilla
kernel it is a modification of dead code AFAIK).

With best wishes,
Vladimir
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