Re: [PATCH] phy: exynos5-drd: Fix PCS_TXDEEMPH mask

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Hi Anton,


On Fri, Sep 19, 2014 at 1:05 PM, Anton Tikhomirov
<av.tikhomirov@xxxxxxxxxxx> wrote:
> According to user manual, pcs_tx_deemph_3p5db field in PHYPARAM1
> register is 6bits wide, so mask value should be 0x3f instead
> of 0x1f.
>
> Signed-off-by: Anton Tikhomirov <av.tikhomirov@xxxxxxxxxxx>
> ---
>  drivers/phy/phy-exynos5-usbdrd.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-
> usbdrd.c
> index 392101c..f421d16 100644
> --- a/drivers/phy/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/phy-exynos5-usbdrd.c
> @@ -99,7 +99,7 @@
>
>  #define EXYNOS5_DRD_PHYPARAM1                  0x20
>
> -#define PHYPARAM1_PCS_TXDEEMPH_MASK            (0x1f << 0)
> +#define PHYPARAM1_PCS_TXDEEMPH_MASK            (0x3f << 0)

use a "_3P5DB" suffix for the macro name ? may sound similar to how UM says.
anyways verified from Exynos5420 user manual.

with that change,
Reviewed-by: Vivek Gautam <gautam.vivek@xxxxxxxxxxx>


[snip]


-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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