> From: dianders@xxxxxxxxxx [mailto:dianders@xxxxxxxxxx] On Behalf Of Doug Anderson > Sent: Thursday, August 07, 2014 1:53 PM > > On Thu, Aug 7, 2014 at 11:26 AM, Paul Zimmerman > <Paul.Zimmerman@xxxxxxxxxxxx> wrote: > >> From: Kever Yang [mailto:kever.yang@xxxxxxxxx] On Behalf Of Kever Yang > >> Sent: Thursday, August 07, 2014 2:35 AM > >> > >> This patch add compatible data for dwc2 controller found on > >> rk3066, rk3188 and rk3288 processors from rockchip. > >> > >> Signed-off-by: Kever Yang <kever.yang@xxxxxxxxxxxxxx> > >> Acked-by: Paul Zimmerman <paulz@xxxxxxxxxxxx> > >> --- > >> > >> Changes in v4: > >> - max_transfer_size change to 65536, this should be enough > >> for most transfer, the hardware auto-detect will set this > >> to 0x7ffff which may make dma_alloc_coherent fail when > >> non-dword aligned buf from driver like usbnet happen. > > > > Hi Kever, > > > > Did you test this change thoroughly? I have vague memories of any > > value above 65535 causing problems, at least on my hardware. And I > > see it is set to 65535 in both pci.c and platform.c. I could be > > wrong, but I thought I should mention it. > > Certainly it is documented in the header file to have a max of 65535: > > * @max_transfer_size: The maximum transfer size supported, in bytes > * 2047 to 65,535 > * Actual maximum value is autodetected and also > * the default. > > ...but looking at the register definition that I see, the size can be > up to 19 bits. A 19-bit transfer far exceeds 65535. Do you remember > what the error was? Certainly I can imagine there being errors with > large calls to dma_alloc_coherent()... It's pretty fuzzy. I think a certain type of transfer (Isoc?) didn't work. But I may be misremembering, the problem could have been with max_packet_count > 255 instead. If you have tested it thoroughly with different types of devices then it's probably OK. -- Paul ��.n��������+%������w��{.n�����{���)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
