> > This patch is to enable USB host controller for Intel Quark X1000. Add
> > pci quirks to adjust the packet buffer in/out threshold value, and
> > ensure EHCI packet buffer i/o threshold value is reconfigured to half.
>
> Please add more detailed description. For example, why is it necessary to
> reconfigure the threshold value?
>
This patch try to reconfigure the threshold value as maximal (0x7F DWord) as possible since the default value is just 0x20 DWord, and I will update the description.
> >
> > +
> > +#define EHCI_INSNREG01 0x84
> > +#define EHCI_INSNREG01_THRESH 0x007F007F /* Threshold value */
>
> What does this magic number mean?
> Would you make it more readable?
0x84 is the register offset, and the high word of '0x007F007F' is the out threshold and the low word is the in threshold. I will use some micros to make it more readable to avoid magic number in PATCH v2.
> > +void usb_set_qrk_bulk_thresh(struct pci_dev *pdev) {
> > + void __iomem *base, *op_reg_base;
> > + u8 cap_length;
> > + u32 val;
> > +
> > + if (!mmio_resource_enabled(pdev, 0))
> > + return;
> > +
> > + base = pci_ioremap_bar(pdev, 0);
> > + if (base == NULL)
> > + return;
> > +
> > + cap_length = readb(base);
> > + op_reg_base = base + cap_length;
> > +
> > + val = readl(op_reg_base + EHCI_INSNREG01);
> > + dev_printk(KERN_INFO, &pdev->dev, "INSNREG01 is 0x%08x\n", val);
> > +
> > + val = EHCI_INSNREG01_THRESH;
> > +
> > + writel(val, op_reg_base + EHCI_INSNREG01);
> > +
> > + val = readl(op_reg_base + EHCI_INSNREG01);
> > + dev_printk(KERN_INFO, &pdev->dev, "INSNREG01 is 0x%08x\n", val);
>
> As Alan Stern said, These INFO message are noisy.
> DEBUG level looks better.
These messages are not necessary, I will remove them.
> Best regards,
> Jingoo Han
>
> > +
> > --
> > 1.7.9.5
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