RE: [RFC 1/4] dwc3: dts: Binding information for an optional property lpm_capable

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> From: Pratyush Anand [mailto:pratyush.anand@xxxxxxxxx]
> Sent: Friday, April 11, 2014 11:06 AM
> 
> On Fri, Apr 11, 2014 at 11:24 PM, Felipe Balbi <balbi@xxxxxx> wrote:
> > On Fri, Apr 11, 2014 at 03:50:03PM +0530, Pratyush Anand wrote:
> >> If a dwc3 host implementation is lpm capable then enable lpm_capable in
> >> device tree.
> >>
> >> Signed-off-by: Pratyush Anand <pratyush.anand@xxxxxx>
> >> ---
> >>  Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
> >>  1 file changed, 2 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> index 7a95c65..a7a48f1 100644
> >> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> @@ -10,6 +10,7 @@ Required properties:
> >>
> >>  Optional properties:
> >>   - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> >> + - lpm-capable: determines if xhci host is lpm capable
> >>
> >>  This is usually a subnode to DWC3 glue to which it is connected.
> >>
> >> @@ -19,4 +20,5 @@ dwc3@4a030000 {
> >>       interrupts = <0 92 4>
> >>       usb-phy = <&usb2_phy>, <&usb3,phy>;
> >>       tx-fifo-resize;
> >> +     lpm-capable;
> >
> > I think there's a way to detect this in runtime but I can't seem to find
> > it on databook. Perhaps check with your IP designer/integrator which
> > HWPARAMS register we can poke to verify core was configured with LPM ?
> 
> I too tried to look into databook first, But could not find. Lets see, what Paul
> says.

Hi guys,

The "Power Management" section of the databook talks about hardware-
controlled LPM. It's section 12.4 in the latest databook. LPM is a
standard xHCI feature, so you can look at the xHCI spec to find the
info about it.

In the xHCI spec, section 4.23.5.1.1 "USB2 LPM Support" says this:

"This section applies only if a USB2 xHCI Supported Protocol Capability
structure (section 7.2) is declared (i.e. the Major Revision field = 02h)."

And if you look at section 7.2.2.1.3.2 "USB2", it shows that bit 19 in
the Protocol Defined field of the USB2 xHCI Supported Protocol Capability
structure indicates whether the controller supports hardware-controlled
LPM.

-- 
Paul

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