On Thu, 9 Dec 2021 12:11:12 -0800 Beau Belgrave <beaub@xxxxxxxxxxxxxxxxxxx> wrote: > I guess I am being paranoid about an architecture that does not have > automatic cache consistency and while the write / read don't happen at > the exact time, they happen close together. Close enough that one CPU > reads the old value from a cache line and gets it wrong. > > I don't believe that is possible on Intel, but I don't know if it's > possible on other architectures (especially older ones). If this was possible, then there would be a lot more bugs out there than this one. For one thing, the file descriptor itself would be freed while accessed. -- Steve
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