The following commit has been merged into the x86/cache branch of tip: Commit-ID: 4d20f38ab6d922dd6b8a33795b6e72516d733eb2 Gitweb: https://git.kernel.org/tip/4d20f38ab6d922dd6b8a33795b6e72516d733eb2 Author: James Morse <james.morse@xxxxxxx> AuthorDate: Tue, 11 Mar 2025 18:37:10 Committer: Borislav Petkov (AMD) <bp@xxxxxxxxx> CommitterDate: Wed, 12 Mar 2025 12:24:30 +01:00 x86/resctrl: Make prefetch_disable_bits belong to the arch code prefetch_disable_bits is set by rdtgroup_locksetup_enter() from a value provided by the architecture, but is largely read by other architecture helpers. Make resctrl_arch_get_prefetch_disable_bits() set prefetch_disable_bits so that it can be isolated to arch-code from where the other arch-code helpers can use its cached value. Signed-off-by: James Morse <james.morse@xxxxxxx> Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> Reviewed-by: Shaopeng Tan <tan.shaopeng@xxxxxxxxxxxxxx> Reviewed-by: Tony Luck <tony.luck@xxxxxxxxx> Reviewed-by: Reinette Chatre <reinette.chatre@xxxxxxxxx> Reviewed-by: Fenghua Yu <fenghuay@xxxxxxxxxx> Reviewed-by: Babu Moger <babu.moger@xxxxxxx> Tested-by: Carl Worth <carl@xxxxxxxxxxxxxxxxxxxxxx> # arm64 Tested-by: Shaopeng Tan <tan.shaopeng@xxxxxxxxxxxxxx> Tested-by: Peter Newman <peternewman@xxxxxxxxxx> Tested-by: Amit Singh Tomar <amitsinght@xxxxxxxxxxx> # arm64 Tested-by: Shanker Donthineni <sdonthineni@xxxxxxxxxx> # arm64 Tested-by: Babu Moger <babu.moger@xxxxxxx> Link: https://lore.kernel.org/r/20250311183715.16445-26-james.morse@xxxxxxx --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 1f42c11..90044a0 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -84,6 +84,8 @@ static const struct class pseudo_lock_class = { */ u64 resctrl_arch_get_prefetch_disable_bits(void) { + prefetch_disable_bits = 0; + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || boot_cpu_data.x86 != 6) return 0; @@ -99,7 +101,8 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 3 DCU IP Prefetcher Disable (R/W) * 63:4 Reserved */ - return 0xF; + prefetch_disable_bits = 0xF; + break; case INTEL_ATOM_GOLDMONT: case INTEL_ATOM_GOLDMONT_PLUS: /* @@ -110,10 +113,11 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 2 DCU Hardware Prefetcher Disable (R/W) * 63:3 Reserved */ - return 0x5; + prefetch_disable_bits = 0x5; + break; } - return 0; + return prefetch_disable_bits; } /** @@ -713,8 +717,7 @@ int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp) * Not knowing the bits to disable prefetching implies that this * platform does not support Cache Pseudo-Locking. */ - prefetch_disable_bits = resctrl_arch_get_prefetch_disable_bits(); - if (prefetch_disable_bits == 0) { + if (resctrl_arch_get_prefetch_disable_bits() == 0) { rdt_last_cmd_puts("Pseudo-locking not supported\n"); return -EINVAL; }
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