The following commit has been merged into the irq/core branch of tip:
Commit-ID: 2631c2b8e5c3406af62b60413ea04e155be9ebcc
Gitweb: https://git.kernel.org/tip/2631c2b8e5c3406af62b60413ea04e155be9ebcc
Author: Inochi Amaoto <inochiama@xxxxxxxxx>
AuthorDate: Thu, 31 Oct 2024 14:08:57 +08:00
Committer: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitterDate: Thu, 07 Nov 2024 00:28:27 +01:00
dt-bindings: interrupt-controller: Add T-HEAD C900 ACLINT SSWI device
Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully
featured T-HEAD ACLINT device. This ACLINT device contains a SSWI device to
support fast S-mode IPI.
Add necessary compatible string for the T-HEAD ACLINT SSWI device.
Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Link: https://lore.kernel.org/all/20241031060859.722258-2-inochiama@xxxxxxxxx
Link: https://www.xrvm.com/product/xuantie/C920
---
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
new file mode 100644
index 0000000..8d33090
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device
+
+maintainers:
+ - Inochi Amaoto <inochiama@xxxxxxxxxxx>
+
+description:
+ The SSWI device is a part of the THEAD ACLINT device. It provides
+ supervisor-level IPI functionality for a set of HARTs on a THEAD
+ platform. It provides a register to set an IPI (SETSSIP) for each
+ HART connected to the SSWI device.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sophgo,sg2044-aclint-sswi
+ - const: thead,c900-aclint-sswi
+
+ reg:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - interrupt-controller
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@94000000 {
+ compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
+ reg = <0x94000000 0x00004000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu1intc 1>,
+ <&cpu2intc 1>,
+ <&cpu3intc 1>,
+ <&cpu4intc 1>;
+ };
+...
|