The following commit has been merged into the ras/core branch of tip: Commit-ID: 754269ccf03d68da15b9e5cdd26a6464b81cec67 Gitweb: https://git.kernel.org/tip/754269ccf03d68da15b9e5cdd26a6464b81cec67 Author: Qiuxu Zhuo <qiuxu.zhuo@xxxxxxxxx> AuthorDate: Fri, 25 Oct 2024 10:45:54 +08:00 Committer: Borislav Petkov (AMD) <bp@xxxxxxxxx> CommitterDate: Mon, 28 Oct 2024 14:27:34 +01:00 x86/mce/intel: Use MCG_BANKCNT_MASK instead of 0xff Use the predefined MCG_BANKCNT_MASK macro instead of the hardcoded 0xff to mask the bank number bits. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@xxxxxxxxx> Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> Reviewed-by: Tony Luck <tony.luck@xxxxxxxxx> Reviewed-by: Nikolay Borisov <nik.borisov@xxxxxxxx> Reviewed-by: Sohil Mehta <sohil.mehta@xxxxxxxxx> Link: https://lore.kernel.org/r/20241025024602.24318-3-qiuxu.zhuo@xxxxxxxxx --- arch/x86/kernel/cpu/mce/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6..b3cd2c6 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static int cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); }
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