The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa
Gitweb: https://git.kernel.org/tip/4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa
Author: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
AuthorDate: Mon, 09 Sep 2024 10:56:11 +02:00
Committer: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitterDate: Wed, 02 Oct 2024 15:12:18 +02:00
irqchip/riscv-imsic: Fix output text of base address
The "per-CPU IDs ... at base ..." info log is outputting a physical
address, not a PPN.
Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices")
Signed-off-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx>
Link: https://lore.kernel.org/all/20240909085610.46625-2-ajones@xxxxxxxxxxxxxxxx
---
drivers/irqchip/irq-riscv-imsic-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c
index 64905e6..c708780 100644
--- a/drivers/irqchip/irq-riscv-imsic-platform.c
+++ b/drivers/irqchip/irq-riscv-imsic-platform.c
@@ -341,7 +341,7 @@ int imsic_irqdomain_init(void)
imsic->fwnode, global->hart_index_bits, global->guest_index_bits);
pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n",
imsic->fwnode, global->group_index_bits, global->group_index_shift);
- pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n",
+ pr_info("%pfwP: per-CPU IDs %d at base address %pa\n",
imsic->fwnode, global->nr_ids, &global->base_addr);
pr_info("%pfwP: total %d interrupts available\n",
imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1));
|