This is obviously nonsense. Fix it.
Fixes: 68b4c6d168c5 ("x86/mce: Switch to new Intel CPU model defines")
Reported-by: Borislav Petkov <bp@xxxxxxxxx>
Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx>
---
Boris: Do you rebase x86/cpu branch in TIP? If so this could be merged
into the broken patch. If not then slap it on top. Risk of bisection
breakage is tiny as this only affects a quirk handling patrol scrub
errors on Skylake and Cascade lake systems.
arch/x86/kernel/cpu/mce/severity.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c
index 7293a1c49050..e7892f11c70f 100644
--- a/arch/x86/kernel/cpu/mce/severity.c
+++ b/arch/x86/kernel/cpu/mce/severity.c
@@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char
continue;
if (s->excp && excp != s->excp)
continue;
- if (s->cpu_vfm && boot_cpu_data.x86_model != s->cpu_vfm)
+ if (s->cpu_vfm && boot_cpu_data.x86_vfm != s->cpu_vfm)
continue;
if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping)
continue;
--
2.44.0
|