The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8248ca30ef89f9cc74ace62ae1b9a22b5f16736c
Gitweb: https://git.kernel.org/tip/8248ca30ef89f9cc74ace62ae1b9a22b5f16736c
Author: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>
AuthorDate: Thu, 07 Mar 2024 01:23:30 +08:00
Committer: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
CommitterDate: Wed, 13 Mar 2024 12:08:59 +01:00
clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
In the RISC-V specification, the stimecmp register doesn't have a default
value. To prevent the timer interrupt from being triggered during timer
initialization, clear the timer interrupt by writing stimecmp with a
maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
Cc: <stable@xxxxxxxxxxxxxxx>
Signed-off-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>
Reviewed-by: Samuel Holland <samuel.holland@xxxxxxxxxx>
Tested-by: Samuel Holland <samuel.holland@xxxxxxxxxx>
Reviewed-by: Atish Patra <atishp@xxxxxxxxxxxx>
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@xxxxxxxxxxxxxxxx
---
drivers/clocksource/timer-riscv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index e66dcbd..79bb9a9 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
+ /* Clear timer interrupt */
+ riscv_clock_event_stop();
+
ce->cpumask = cpumask_of(cpu);
ce->irq = riscv_clock_event_irq;
if (riscv_timer_cannot_wake_cpu)
|