* tip-bot2 for Borislav Petkov (AMD) <tip-bot2@xxxxxxxxxxxxx> wrote: > /* AMD Last Branch Record MSRs */ > #define MSR_AMD64_LBR_SELECT 0xc000010e > > +/* Zen4 */ > +#define MSR_ZEN4_BP_CFG 0xc001102e > +#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 > > +/* Zen 2 */ > #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 > #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) > > +/* Fam 17h MSRs */ > +#define MSR_F17H_IRPERF 0xc00000e9 Yeah, so these latest AMD MSR definitions in <asm/msr-index.h> are pretty confused, they list MSRs in the following order: Zen 4 Zen 2 Fam 19h // resolution in tip:master Fam 17h where perf/core added a Fam 19h section a couple of days ago ... While in reality: Zen 2 == Fam 17h Zen 4 == Fam 19h So it's confusing to list these separately and out of order. So in resolving the conflict in perf/core I updated this section to read: /* Fam 19h (Zen 4) MSRs */ #define MSR_F19H_UMC_PERF_CTL 0xc0010800 #define MSR_F19H_UMC_PERF_CTR 0xc0010801 #define MSR_ZEN4_BP_CFG 0xc001102e #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 /* Fam 17h (Zen 2) MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) This doesn't change the definitions themselves, only merges the comments and the sections, (to keep the Git conflict resolution non-evil), but arguably once perf/core goes upstream, we should probably unify the naming to follow the existing nomenclature, which is, starting at around F15H, the following: MSR_F15H_ MSR_F16H_ MSR_F17H_ MSR_F19H_ Or are the MSRs named ZEN2 and ZEN4 in AMD SDMs, which we should follow? Anyway, something to keep in mind. Thanks, Ingo
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