The following commit has been merged into the x86/cpu branch of tip: Commit-ID: a9dc9ec5a1fafc3d2fe7a7b594eefaeaccf89a6b Gitweb: https://git.kernel.org/tip/a9dc9ec5a1fafc3d2fe7a7b594eefaeaccf89a6b Author: Kim Phillips <kim.phillips@xxxxxxx> AuthorDate: Tue, 24 Jan 2023 10:33:14 -06:00 Committer: Borislav Petkov (AMD) <bp@xxxxxxxxx> CommitterDate: Wed, 25 Jan 2023 12:36:34 +01:00 x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature The "Processor ignores nested data breakpoints" feature was being open-coded for KVM. Add the feature to its newly introduced CPUID leaf 0x80000021 EAX proper. Signed-off-by: Kim Phillips <kim.phillips@xxxxxxx> Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> Acked-by: Sean Christopherson <seanjc@xxxxxxxxxx> Link: https://lore.kernel.org/r/20230124163319.2277355-4-kim.phillips@xxxxxxx --- arch/x86/include/asm/cpufeatures.h | 3 +++ arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b890058..1b2d40a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -427,6 +427,9 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ + /* * BUG word(s) */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index f3edc35..aa3a6dc 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,7 +742,7 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - BIT(0) /* NO_NESTED_DATA_BP */ | + F(NO_NESTED_DATA_BP) | BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ | BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ );
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