The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 0205f8a738ab9e62d849e88e543cfa6ce4c13163 Gitweb: https://git.kernel.org/tip/0205f8a738ab9e62d849e88e543cfa6ce4c13163 Author: Ricardo Cañuelo <ricardo.canuelo@xxxxxxxxxxxxx> AuthorDate: Fri, 01 Apr 2022 09:45:17 +02:00 Committer: Borislav Petkov <bp@xxxxxxx> CommitterDate: Tue, 05 Apr 2022 21:55:57 +02:00 x86/speculation/srbds: Do not try to turn mitigation off when not supported When SRBDS is mitigated by TSX OFF, update_srbds_msr() will still read and write to MSR_IA32_MCU_OPT_CTRL even when that MSR is not supported due to not having loaded the appropriate microcode. Check for X86_FEATURE_SRBDS_CTRL which is set only when the respective microcode which adds MSR_IA32_MCU_OPT_CTRL is loaded. Based on a patch by Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx>. [ bp: Massage commit message. ] Suggested-by: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx> Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@xxxxxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Link: https://lore.kernel.org/r/20220401074517.1848264-1-ricardo.canuelo@xxxxxxxxxxxxx --- arch/x86/kernel/cpu/bugs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6296e1e..d879a6c 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -446,6 +446,13 @@ void update_srbds_msr(void) if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) return; + /* + * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX + * being disabled and it hasn't received the SRBDS MSR microcode. + */ + if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) + return; + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); switch (srbds_mitigation) {
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