The following commit has been merged into the perf/core branch of tip: Commit-ID: d903b6d029d66e6478562d75ea18d89098f7b7e8 Gitweb: https://git.kernel.org/tip/d903b6d029d66e6478562d75ea18d89098f7b7e8 Author: Pu Wen <puwen@xxxxxxxx> AuthorDate: Mon, 20 Jul 2020 16:22:05 +08:00 Committer: Ingo Molnar <mingo@xxxxxxxxxx> CommitterDate: Tue, 28 Jul 2020 13:34:20 +02:00 perf/x86/rapl: Add Hygon Fam18h RAPL support Hygon Family 18h(Dhyana) support RAPL in bit 14 of CPUID 0x80000007 EDX, and has MSRs RAPL_PWR_UNIT/CORE_ENERGY_STAT/PKG_ENERGY_STAT. So add Hygon Dhyana Family 18h support for RAPL. The output is available via the energy-pkg pseudo event: $ perf stat -a -I 1000 --per-socket -e power/energy-pkg/ [ mingo: Tidied up the initializers. ] Signed-off-by: Pu Wen <puwen@xxxxxxxx> Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> Link: https://lore.kernel.org/r/20200720082205.1307-1-puwen@xxxxxxxx --- arch/x86/events/rapl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 0f2bf59..68b3882 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -787,7 +787,8 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl), - X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h), + X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h), + X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h), {}, }; MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);
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