The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: d727be7bbf7b68ccc18a3278469325d8f486d75b
Gitweb: https://git.kernel.org/tip/d727be7bbf7b68ccc18a3278469325d8f486d75b
Author: Atish Patra <atish.patra@xxxxxxx>
AuthorDate: Thu, 02 Apr 2020 18:46:09 -07:00
Committer: Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Fri, 17 Apr 2020 08:59:28 +01:00
irqchip/sifive-plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.
Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20200403014609.71831-1-atish.patra@xxxxxxx
---
drivers/irqchip/irq-sifive-plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c34fb3a..d0a71fe 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -56,7 +56,7 @@
#define CONTEXT_THRESHOLD 0x00
#define CONTEXT_CLAIM 0x04
-#define PLIC_DISABLE_THRESHOLD 0xf
+#define PLIC_DISABLE_THRESHOLD 0x7
#define PLIC_ENABLE_THRESHOLD 0
struct plic_priv {
|