The following commit has been merged into the perf/core branch of tip: Commit-ID: 0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 Gitweb: https://git.kernel.org/tip/0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 Author: Kan Liang <kan.liang@xxxxxxxxxxxxxxx> AuthorDate: Tue, 28 Jan 2020 10:31:19 -08:00 Committer: Ingo Molnar <mingo@xxxxxxxxxx> CommitterDate: Tue, 11 Feb 2020 13:17:50 +01:00 perf/x86/msr: Add Tremont support Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also supported. Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx> Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> Reviewed-by: Andi Kleen <ak@xxxxxxxxxxxxxxx> Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@xxxxxxxxxxxxxxx --- arch/x86/events/msr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 6f86650..a949f6f 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT: case INTEL_FAM6_ATOM_GOLDMONT_D: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_FAM6_ATOM_TREMONT_D: + case INTEL_FAM6_ATOM_TREMONT: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM:
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