The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 9774a96f785bf0fa6d956ce33300463f1704dbeb Gitweb: https://git.kernel.org/tip/9774a96f785bf0fa6d956ce33300463f1704dbeb Author: Babu Moger <Babu.Moger@xxxxxxx> AuthorDate: Tue, 05 Nov 2019 21:25:40 Committer: Borislav Petkov <bp@xxxxxxx> CommitterDate: Thu, 07 Nov 2019 11:16:44 +01:00 x86/umip: Make the comments vendor-agnostic AMD 2nd generation EPYC processors also support the UMIP feature. Make the comments vendor-agnostic. Signed-off-by: Babu Moger <babu.moger@xxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Cc: Andy Lutomirski <luto@xxxxxxxxxx> Cc: "H. Peter Anvin" <hpa@xxxxxxxxx> Cc: Ingo Molnar <mingo@xxxxxxxxxx> Cc: Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> Cc: "x86@xxxxxxxxxx" <x86@xxxxxxxxxx> Link: https://lkml.kernel.org/r/157298913784.17462.12654728938970637305.stgit@xxxxxxxxxxxxxxxxxxx --- arch/x86/kernel/umip.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index 548fefe..8ccef6c 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -1,6 +1,6 @@ /* - * umip.c Emulation for instruction protected by the Intel User-Mode - * Instruction Prevention feature + * umip.c Emulation for instruction protected by the User-Mode Instruction + * Prevention feature * * Copyright (c) 2017, Intel Corporation. * Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx> @@ -18,10 +18,10 @@ /** DOC: Emulation for User-Mode Instruction Prevention (UMIP) * - * The feature User-Mode Instruction Prevention present in recent Intel - * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR) - * from being executed with CPL > 0. Otherwise, a general protection fault is - * issued. + * User-Mode Instruction Prevention is a security feature present in recent + * x86 processors that, when enabled, prevents a group of instructions (SGDT, + * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general + * protection fault if the instruction is executed with CPL > 0. * * Rather than relaying to the user space the general protection fault caused by * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be
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