The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 9d40b85bb46a99bc95dad3a07787da93b0a018e9 Gitweb: https://git.kernel.org/tip/9d40b85bb46a99bc95dad3a07787da93b0a018e9 Author: Babu Moger <babu.moger@xxxxxxx> AuthorDate: Mon, 07 Oct 2019 15:48:39 -05:00 Committer: Borislav Petkov <bp@xxxxxxx> CommitterDate: Tue, 08 Oct 2019 09:28:37 +02:00 x86/cpufeatures: Add feature bit RDPRU on AMD AMD Zen 2 introduces a new RDPRU instruction which is used to give access to some processor registers that are typically only accessible when the privilege level is zero. ECX is used as the implicit register to specify which register to read. RDPRU places the specified register’s value into EDX:EAX. For example, the RDPRU instruction can be used to read MPERF and APERF at CPL > 0. Add the feature bit so it is visible in /proc/cpuinfo. Details are available in the AMD64 Architecture Programmer’s Manual: https://www.amd.com/system/files/TechDocs/24594.pdf Signed-off-by: Babu Moger <babu.moger@xxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Cc: Aaron Lewis <aaronlewis@xxxxxxxxxx> Cc: ak@xxxxxxxxxxxxxxx Cc: Fenghua Yu <fenghua.yu@xxxxxxxxx> Cc: "H. Peter Anvin" <hpa@xxxxxxxxx> Cc: Ingo Molnar <mingo@xxxxxxxxxx> Cc: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> Cc: "Peter Zijlstra (Intel)" <peterz@xxxxxxxxxxxxx> Cc: robert.hu@xxxxxxxxxxxxxxx Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> Cc: Thomas Hellstrom <thellstrom@xxxxxxxxxx> Cc: x86-ml <x86@xxxxxxxxxx> Link: https://lkml.kernel.org/r/20191007204839.5727.10803.stgit@localhost.localdomain --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0652d3e..1db10a1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -292,6 +292,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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