Commit-ID: f8c0e061cb83bd528ff0843e717bcebc846d4838
Gitweb: https://git.kernel.org/tip/f8c0e061cb83bd528ff0843e717bcebc846d4838
Author: Tony W Wang-oc <TonyWWang-oc@xxxxxxxxxxx>
AuthorDate: Tue, 18 Jun 2019 08:37:29 +0000
Committer: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitDate: Sat, 22 Jun 2019 11:45:58 +0200
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@xxxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: "hpa@xxxxxxxxx" <hpa@xxxxxxxxx>
Cc: "gregkh@xxxxxxxxxxxxxxxxxxx" <gregkh@xxxxxxxxxxxxxxxxxxx>
Cc: "rjw@xxxxxxxxxxxxx" <rjw@xxxxxxxxxxxxx>
Cc: "lenb@xxxxxxxxxx" <lenb@xxxxxxxxxx>
Cc: David Wang <DavidWang@xxxxxxxxxxx>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@xxxxxxxxxxx>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@xxxxxxxxxxx>
Cc: "Herry Yang(BJ-RD)" <HerryYang@xxxxxxxxxxx>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@xxxxxxxxxxx
---
arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484988fd..caf2edccbad2 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
c->x86_stepping >= 0x0e))
flags->bm_check = 1;
}
+
+ if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ /*
+ * All Zhaoxin CPUs that support C3 share cache.
+ * And caches should not be flushed by software while
+ * entering C3 type state.
+ */
+ flags->bm_check = 1;
+ /*
+ * On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+ * So, set bm_control to zero to indicate that ARB_DISABLE
+ * is not required while entering C3 type state.
+ */
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
|