Commit-ID: c927d74ec0319abb0b232adf9dbe4e7be3791328
Gitweb: https://git.kernel.org/tip/c927d74ec0319abb0b232adf9dbe4e7be3791328
Author: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>
AuthorDate: Thu, 22 Mar 2018 16:15:23 +0100
Committer: Marc Zyngier <marc.zyngier@xxxxxxx>
CommitDate: Thu, 22 Mar 2018 15:52:27 +0000
dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
Add the Device Tree binding documentation for the Microsemi Ocelot
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Acked-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>
Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
---
...{ingenic,intc.txt => mscc,ocelot-icpu-intr.txt} | 26 +++++++++-------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
similarity index 51%
copy from Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
copy to Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index 5f89fb635a1b..b47a8a02b17b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,12 +1,8 @@
-Ingenic SoC Interrupt Controller
+Microsemi Ocelot SoC ICPU Interrupt Controller
Required properties:
-- compatible : should be "ingenic,<socname>-intc". Valid strings are:
- ingenic,jz4740-intc
- ingenic,jz4770-intc
- ingenic,jz4775-intc
- ingenic,jz4780-intc
+- compatible : should be "mscc,ocelot-icpu-intr"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
@@ -16,13 +12,11 @@ Required properties:
Example:
-intc: interrupt-controller@10001000 {
- compatible = "ingenic,jz4740-intc";
- reg = <0x10001000 0x14>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
-};
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
--
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