On October 16, 2016 7:22:33 AM PDT, Borislav Petkov <bp@xxxxxxxxx> wrote: >On Sun, Oct 16, 2016 at 04:21:49AM -0700, tip-bot for Piotr Luc wrote: >> Commit-ID: a518dcc82b6162009c8ca3d169fe61c81536ff17 >> Gitweb: >http://git.kernel.org/tip/a518dcc82b6162009c8ca3d169fe61c81536ff17 >> Author: Piotr Luc <piotr.luc@xxxxxxxxx> >> AuthorDate: Wed, 12 Oct 2016 19:57:31 +0200 >> Committer: Ingo Molnar <mingo@xxxxxxxxxx> >> CommitDate: Sun, 16 Oct 2016 11:32:11 +0200 >> >> x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features >> >> AVX512_4VNNIW - Vector instructions for deep learning enhanced word >> variable precision. >> AVX512_4FMAPS - Vector instructions for deep learning floating-point >> single precision. >> >> The new instructions are to be used in future Intel Xeon & Xeon Phi >> processors. >> >> The spec can be found in Intel Software Developer Manual or in >> Instruction Set Extensions Programming Reference. See >> >https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf. >> >> Signed-off-by: Piotr Luc <piotr.luc@xxxxxxxxx> >> Reviewed-by: Dave Hansen <dave.hansen@xxxxxxxxx> >> Cc: Andy Lutomirski <luto@xxxxxxxxxx> >> Cc: Borislav Petkov <bp@xxxxxxxxx> >> Cc: Brian Gerst <brgerst@xxxxxxxxx> >> Cc: Denys Vlasenko <dvlasenk@xxxxxxxxxx> >> Cc: H. Peter Anvin <hpa@xxxxxxxxx> >> Cc: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> >> Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> >> Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx> >> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> >> Link: >http://lkml.kernel.org/r/20161012175731.29619-1-piotr.luc@xxxxxxxxx >> Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> > >... > >> diff --git a/arch/x86/include/asm/cpufeatures.h >b/arch/x86/include/asm/cpufeatures.h >> index 1188bc8..6697b75 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -12,7 +12,7 @@ >> /* >> * Defines x86 CPU feature bits >> */ >> -#define NCAPINTS 18 /* N 32-bit words worth of info */ >> +#define NCAPINTS 19 /* N 32-bit words worth of info */ >> #define NBUGINTS 1 /* N 32-bit bug flags */ >> >> /* >> @@ -285,6 +285,10 @@ >> #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error >containment and recovery */ >> #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ >> >> +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), word >18 */ >> +#define X86_FEATURE_AVX512_4VNNIW (18*32+2) /* AVX-512 Neural >Network Instructions */ >> +#define X86_FEATURE_AVX512_4FMAPS (18*32+3) /* AVX-512 Multiply >Accumulation Single precision */ > >This is getting ridiculous: we keep adding new leafs to >->x86_capability, thus bloating cpuinfo_x86 but then it is not even >worth it - this patch defines only two bits. > >I know, I know, it is a CPUID leaf of features, we will need them, >yadda >yadda but until we do, I'd suggest these all new feature bits to to >init_scattered_cpuid_features() and be carved out to a leaf of their >own *only* when we really, actually add them and fill up that leaf. >Otherwise, we have one fat and sparse x86_capability array. No, please. That would be worse than the disease. -- Sent from my Android device with K-9 Mail. Please excuse my brevity. -- To unsubscribe from this list: send the line "unsubscribe linux-tip-commits" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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