Commit-ID: 1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596
Gitweb: http://git.kernel.org/tip/1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596
Author: Tirumalesh Chalamarla <tchalamarla@xxxxxxxxxxxxxxxxxx>
AuthorDate: Thu, 4 Feb 2016 10:45:25 -0800
Committer: Marc Zyngier <marc.zyngier@xxxxxxx>
CommitDate: Thu, 11 Feb 2016 10:20:02 +0000
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:
4.1.1 Physical CPU Interface:
The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
on the state of a returned INTID are not guaranteed
to be visible until after the execution of a DSB.
Not having this could result in missed interrupts, so let's add the
required barrier.
[Marc: fixed commit message]
Acked-by: Marc Zyngier <marc.zyngier@xxxxxxx>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
---
arch/arm64/include/asm/arch_gicv3.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 2731d3b..8ec88e5 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
u64 irqstat;
asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+ dsb(sy);
return irqstat;
}
--
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