Commit-ID: ccc414f83914178c7ab04ac4d4f0331fe4c37231
Gitweb: http://git.kernel.org/tip/ccc414f83914178c7ab04ac4d4f0331fe4c37231
Author: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
AuthorDate: Fri, 28 Jun 2013 11:45:15 +0200
Committer: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitDate: Fri, 28 Jun 2013 12:56:04 +0200
genirq: Add the generic chip to the genirq docbook
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
---
Documentation/DocBook/genericirq.tmpl | 13 +++++++++++++
kernel/irq/generic-chip.c | 11 ++++++-----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/Documentation/DocBook/genericirq.tmpl b/Documentation/DocBook/genericirq.tmpl
index b342234..d16d21b 100644
--- a/Documentation/DocBook/genericirq.tmpl
+++ b/Documentation/DocBook/genericirq.tmpl
@@ -464,6 +464,19 @@ if (desc->irq_data.chip->irq_eoi)
protected via desc->lock, by the generic layer.
</para>
</chapter>
+
+ <chapter id="genericchip">
+ <title>Generic interrupt chip</title>
+ <para>
+ To avoid copies of identical implementations of irq chips the
+ core provides a configurable generic interrupt chip
+ implementation. Developers should check carefuly whether the
+ generic chip fits their needs before implementing the same
+ functionality slightly different themself.
+ </para>
+!Ekernel/irq/generic-chip.c
+ </chapter>
+
<chapter id="structs">
<title>Structures</title>
<para>
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 76ea748..1c39ecc 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -45,7 +45,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
}
/**
- * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
+ * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
* @d: irq_data
*
* Chip has a single mask register. Values of this register are cached
@@ -65,7 +65,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
/**
- * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
+ * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
* @d: irq_data
*
* Chip has a single mask register. Values of this register are cached
@@ -167,7 +167,8 @@ void irq_gc_eoi(struct irq_data *d)
/**
* irq_gc_set_wake - Set/clr wake bit for an interrupt
- * @d: irq_data
+ * @d: irq_data
+ * @on: Indicates whether the wake bit should be set or cleared
*
* For chips where the wake from suspend functionality is not
* configured in a separate register and the wakeup active state is
@@ -339,7 +340,7 @@ EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
*/
static struct lock_class_key irq_nested_lock_class;
-/**
+/*
* irq_map_generic_chip - Map a generic chip for an irq domain
*/
static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
@@ -454,7 +455,7 @@ EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
/**
* irq_setup_alt_chip - Switch to alternative chip
* @d: irq_data for this interrupt
- * @type Flow type to be initialized
+ * @type: Flow type to be initialized
*
* Only to be called from chip->irq_set_type() callbacks.
*/
--
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