Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update ucode on Intel's CPU
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- Subject: Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update ucode on Intel's CPU
- From: "H. Peter Anvin" <hpa@xxxxxxxxxxxxxxx>
- Date: Wed, 19 Dec 2012 20:21:29 -0800
- Cc: "H. Peter Anvin" <hpa@xxxxxxxxx>, Borislav Petkov <bp@xxxxxxxxx>, Yinghai Lu <yinghai@xxxxxxxxxx>, "Yu, Fenghua" <fenghua.yu@xxxxxxxxx>, "mingo@xxxxxxxxxx" <mingo@xxxxxxxxxx>, "linux-kernel@xxxxxxxxxxxxxxx" <linux-kernel@xxxxxxxxxxxxxxx>, "tglx@xxxxxxxxxxxxx" <tglx@xxxxxxxxxxxxx>, "linux-tip-commits@xxxxxxxxxxxxxxx" <linux-tip-commits@xxxxxxxxxxxxxxx>, Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>, Stefano Stabellini <Stefano.Stabellini@xxxxxxxxxxxxx>
- In-reply-to: <20121220041621.GA23609@jshin-Toonie>
- User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0
On 12/19/2012 08:16 PM, Jacob Shin wrote:
>
> Not exactly sure why the wierd boundaries, I'll have to ask the BIOS
> side folks to be sure. But if I were to guess ..
>
> Here is the NUMA spew out, physically there is 128 GB connected to
> each memory controller node. The PCI MMIO region starts at 0xc8000000.
> 4 GB - 0xc8000000 = 0x3800000 (896 MB). So we loose 896 MB due to PCI
> MMIO hole, so the first node ends at 128 GB + 896 MB to talk to all of
> 128 GB off of the first memory controller, and hence the weird 896 MB
> offset.
>
It would obviously be better if the slack were at the end of the total
memory, instead of end of the < 1T range. If the PCI MMIO hole were a
power of 2 (e.g. 1G) that would also reduce the likelihood of problems
and reduce MTRR pressure.
-hpa
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