Commit-ID: 7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a
Gitweb: http://git.kernel.org/tip/7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a
Author: Vince Weaver <vincent.weaver@xxxxxxxxx>
AuthorDate: Fri, 19 Oct 2012 17:30:01 -0400
Committer: Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Wed, 24 Oct 2012 10:31:57 +0200
perf/x86: Fix P6 FP_ASSIST event constraint
According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only,
not Counter 0.
Tested on a Pentium II.
Signed-off-by: Vince Weaver <vincent.weaver@xxxxxxxxx>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@xxxxxxxxx>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191728570.14552@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
arch/x86/kernel/cpu/perf_event_p6.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index e4dd0f7..0ff5f7f 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -34,7 +34,7 @@ static struct event_constraint p6_event_constraints[] =
{
INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
- INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
+ INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
--
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