Commit-ID: 8045a4c293d36c61656a20d581b11f7f0cd7acd5
Gitweb: http://git.kernel.org/tip/8045a4c293d36c61656a20d581b11f7f0cd7acd5
Author: Robert Richter <robert.richter@xxxxxxx>
AuthorDate: Tue, 7 Jul 2009 19:30:25 +0200
Committer: Robert Richter <robert.richter@xxxxxxx>
CommitDate: Tue, 14 Jul 2009 15:30:03 +0200
x86/oprofile: Fix cast of counter value
When casting the counter value to a 64 bit value in 32 bit mode, sign
extension may lead to broken counter values. This patch fixes this by
casting to (u64) instead of (s64).
Signed-off-by: Robert Richter <robert.richter@xxxxxxx>
---
arch/x86/oprofile/op_model_amd.c | 4 ++--
arch/x86/oprofile/op_model_p4.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index e95268e..7ca8306 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -111,7 +111,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
if (counter_config[i].enabled && msrs->counters[i].addr) {
reset_value[i] = counter_config[i].count;
wrmsrl(msrs->counters[i].addr,
- -(s64)counter_config[i].count);
+ -(u64)counter_config[i].count);
rdmsrl(msrs->controls[i].addr, val);
val &= model->reserved;
val |= op_x86_get_ctrl(model, &counter_config[i]);
@@ -237,7 +237,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
if (val & OP_CTR_OVERFLOW)
continue;
oprofile_add_sample(regs, i);
- wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]);
+ wrmsrl(msrs->counters[i].addr, -(u64)reset_value[i]);
}
op_amd_handle_ibs(regs, msrs);
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index f01e53b..9db9e36 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -580,7 +580,7 @@ static void p4_setup_ctrs(struct op_x86_model_spec const *model,
reset_value[i] = counter_config[i].count;
pmc_setup_one_p4_counter(i);
wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address,
- -(s64)counter_config[i].count);
+ -(u64)counter_config[i].count);
} else {
reset_value[i] = 0;
}
@@ -625,11 +625,11 @@ static int p4_check_ctrs(struct pt_regs * const regs,
if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) {
oprofile_add_sample(regs, i);
wrmsrl(p4_counters[real].counter_address,
- -(s64)reset_value[i]);
+ -(u64)reset_value[i]);
CCCR_CLEAR_OVF(low);
wrmsr(p4_counters[real].cccr_address, low, high);
wrmsrl(p4_counters[real].counter_address,
- -(s64)reset_value[i]);
+ -(u64)reset_value[i]);
}
}
--
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