Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain support to use NMI-safe methods
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- Subject: Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain support to use NMI-safe methods
- From: "H. Peter Anvin" <hpa@xxxxxxxxx>
- Date: Mon, 15 Jun 2009 11:39:47 -0700
- Cc: Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxx>, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>, mingo@xxxxxxxxxx, paulus@xxxxxxxxx, acme@xxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, a.p.zijlstra@xxxxxxxxx, penberg@xxxxxxxxxxxxxx, vegard.nossum@xxxxxxxxx, efault@xxxxxx, jeremy@xxxxxxxx, npiggin@xxxxxxx, tglx@xxxxxxxxxxxxx, linux-tip-commits@xxxxxxxxxxxxxxx
- In-reply-to: <20090615182348.GC11248@xxxxxxx>
- References: <tip-74193ef0ecab92535c8517f082f1f50504526c9b@xxxxxxxxxxxxxx> <alpine.LFD.2.01.0906151007560.3305@xxxxxxxxxxxxxxxxxxxxx> <20090615171845.GA7664@xxxxxxx> <alpine.LFD.2.01.0906151029160.3305@xxxxxxxxxxxxxxxxxxxxx> <20090615180527.GB4201@Krystal> <20090615182348.GC11248@xxxxxxx>
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Ingo Molnar wrote:
> * Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxx> wrote:
>
>> Hrm, would it be possible to save the c2 register upon nmi handler
>> entry and restore it before iret instead ? This would ensure a
>> nmi-interrupted page fault handler would continue what it was
>> doing with a non-corrupted cr2 register after returning from nmi.
>>
>> Plus, this involves no modification to the page fault handler fast
>> path.
>
> I guess this kind of nesting would work too - assuming the cr2 can
> be written to robustly.
>
> And i suspect CPU makers pull off a few tricks to stage the cr2 info
> away from the page fault entry execution asynchronously, so i'd not
> be surprised if writing to it uncovered unknown-so-far side-effects
> in CPU implementations.
>
I wouldn't actually expect that, *as long as* there is serialization
between the cr2 write and the cr2 read.
-hpa
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