Commit-ID: b5e8acf66ff5db707c7e08df49fdf6b415878442
Gitweb: http://git.kernel.org/tip/b5e8acf66ff5db707c7e08df49fdf6b415878442
Author: "Peter Zijlstra" <peterz@xxxxxxxxxxxxx>
AuthorDate: Thu, 5 Mar 2009 20:34:21 +0100
Commit: Ingo Molnar <mingo@xxxxxxx>
CommitDate: Thu, 5 Mar 2009 20:37:21 +0100
perfcounters: IRQ and NMI support on AMD CPUs, fix
The BKGD suggests that counter width on AMD CPUs is 48 for all
existing models (it certainly is for mine).
Signed-off-by: Ingo Molnar <mingo@xxxxxxx>
---
arch/x86/kernel/cpu/perf_counter.c | 16 ++--------------
1 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 6ebe9ab..f585371 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -959,20 +959,8 @@ static struct pmc_x86_ops *pmc_amd_init(void)
nr_counters_generic = 4;
nr_counters_fixed = 0;
- counter_value_mask = ~0ULL;
-
- rdmsrl(MSR_K7_PERFCTR0, old);
- wrmsrl(MSR_K7_PERFCTR0, counter_value_mask);
- /*
- * read the truncated mask
- */
- rdmsrl(MSR_K7_PERFCTR0, counter_value_mask);
- wrmsrl(MSR_K7_PERFCTR0, old);
-
- bits = 32 + fls(counter_value_mask >> 32);
- if (bits == 32)
- bits = fls((u32)counter_value_mask);
- counter_value_bits = bits;
+ counter_value_mask = 0x0000FFFFFFFFFFFFULL;
+ counter_value_bits = 48;
pr_info("AMD Performance Monitoring support detected.\n");
--
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