On Thu, Mar 6, 2025 at 6:06 AM Prathamesh Shete <pshete@xxxxxxxxxx> wrote: > Tegra devices have an 'sfsel' bit field that determines whether a pin > operates in SFIO (Special Function I/O) or GPIO mode. Currently, > tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. > > However, tegra_pinctrl_set_mux() can be called independently in certain > code paths where gpio_disable_free() is not invoked. In such cases, failing > to set the SFIO mode could lead to incorrect pin configurations, resulting > in functional issues for peripherals relying on SFIO. > > This patch ensures that whenever set_mux() is called, the SFIO mode is > correctly set in the Mux Register if the 'sfsel' bit is present. This > prevents situations where the pin remains in GPIO mode despite being > configured for SFIO use. > > Fixes: 59b67585e242 ("pinctrl: add a driver for NVIDIA Tegra") > Signed-off-by: Prathamesh Shete <pshete@xxxxxxxxxx> Patch applied. I can't tell how urgent this patch is so I have applied it for next for the moment. Yours, Linus Walleij