On Fri, Mar 07, 2025 at 04:11:19PM +0000, Jon Hunter wrote: > Hi Russell, > > On 06/03/2025 15:23, Russell King (Oracle) wrote: > > Hi, > > > > This is a second approach to solving the STMMAC reset issues caused by > > the lack of receive clock from the PHY where the media is in low power > > mode with a PHY that supports receive clock-stop. > > > > The first approach centred around only addressing the issue in the > > resume path, but it seems to also happen when the platform glue module > > is removed and re-inserted (Jon - can you check whether that's also > > the case for you please?) > > > > As this is more targetted, I've dropped the patches from this series > > which move the call to phylink_resume(), so the link may still come > > up too early on resume - but that's something I also intend to fix. > > > > This is experimental - so I value test reports for this change. > > > The subject indicates 3 patches, but I only see 2 patches? Can you confirm > if there are 2 or 3? Yes, 2 patches is correct. > So far I have only tested to resume case with the 2 patches to make that > that is working but on Tegra186, which has been the most problematic, it is > not working reliably on top of next-20250305. To confirm, you're seeing stmmac_reset() sporadically timing out on resume even with these patches appled? That's rather disappointing. Do either of the two attached diffs make any difference? Thanks for testing! -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8d3cae5b43c5..63d30e09c095 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3108,9 +3108,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) priv->plat->dma_cfg->atds = 1; /* Note that the PHY clock must be running for reset to complete. */ - phylink_rx_clk_stop_block(priv->phylink); ret = stmmac_reset(priv, priv->ioaddr); - phylink_rx_clk_stop_unblock(priv->phylink); if (ret) { netdev_err(priv->dev, "Failed to reset the dma\n"); return ret; @@ -3480,7 +3478,9 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) phylink_pcs_pre_init(priv->phylink, priv->hw->phylink_pcs); /* DMA initialization and SW reset */ + phylink_rx_clk_stop_block(priv->phylink); ret = stmmac_init_dma_engine(priv); + phylink_rx_clk_stop_unblock(priv->phylink); if (ret < 0) { netdev_err(priv->dev, "%s: DMA engine initialization failed\n", __func__);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8d3cae5b43c5..bebc9f98c875 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3108,9 +3108,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) priv->plat->dma_cfg->atds = 1; /* Note that the PHY clock must be running for reset to complete. */ - phylink_rx_clk_stop_block(priv->phylink); ret = stmmac_reset(priv, priv->ioaddr); - phylink_rx_clk_stop_unblock(priv->phylink); if (ret) { netdev_err(priv->dev, "Failed to reset the dma\n"); return ret; @@ -4045,7 +4043,9 @@ static int __stmmac_open(struct net_device *dev, } } + phylink_rx_clk_stop_block(priv->phylink); ret = stmmac_hw_setup(dev, true); + phylink_rx_clk_stop_unblock(priv->phylink); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); goto init_error; @@ -7949,7 +7949,9 @@ int stmmac_resume(struct device *dev) stmmac_free_tx_skbufs(priv); stmmac_clear_descriptors(priv, &priv->dma_conf); + phylink_rx_clk_stop_block(priv->phylink); stmmac_hw_setup(ndev, false); + phylink_rx_clk_stop_unblock(priv->phylink); stmmac_init_coalesce(priv); stmmac_set_rx_mode(ndev);