On Thu, Feb 06, 2025 at 09:17:21AM -0400, Jason Gunthorpe wrote:
> On Wed, Feb 05, 2025 at 09:30:05PM -0800, Tomasz Jeznach wrote:
> > > @@ -161,9 +163,8 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu,
> > > } else {
> > > do {
> > > const size_t queue_size = entry_size << (logsz + 1);
> > > - const int order = get_order(queue_size);
> > >
> > > - queue->base = riscv_iommu_get_pages(iommu, order);
> > > + queue->base = riscv_iommu_get_pages(iommu, queue_size);
> > > queue->phys = __pa(queue->base);
> >
> > All allocations must be 4k aligned, including sub-page allocs.
>
> Oh weird, so it requires 4k alignment but the HW can refuse to support
> a 4k queue length?
>
Spec allows that. Also, hardware accepts only physical page number (so far PAGE_SIZE == 4K
for riscv) of the base address, ignoring page offset.
> I changed it to this:
>
> + queue->base = riscv_iommu_get_pages(
> + iommu, max(queue_size, SZ_4K));
>
LGTM
> > > } while (!queue->base && logsz-- > 0);
> > > }
> > > @@ -618,7 +619,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm
> > > break;
> > > }
> > >
> > > - ptr = riscv_iommu_get_pages(iommu, 0);
> > > + ptr = riscv_iommu_get_pages(iommu, PAGE_SIZE);
> > > if (!ptr)
> > > return NULL;
> > >
> > > @@ -698,7 +699,7 @@ static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu)
> > > }
> > >
> > > if (!iommu->ddt_root) {
> > > - iommu->ddt_root = riscv_iommu_get_pages(iommu, 0);
> > > + iommu->ddt_root = riscv_iommu_get_pages(iommu, PAGE_SIZE);
> > > iommu->ddt_phys = __pa(iommu->ddt_root);
> > > }
>
> Should these be SZ_4K as well or PAGE_SIZE?
>
SZ_4K. For now iommu/risc-v hardware always assumes PAGE_SIZE == 4K.
> Thanks,
> Jason
Thanks,
- Tomasz
