Am Freitag, dem 24.01.2025 um 14:15 +0100 schrieb Thierry Reding: > [...] > > The dma-coherent property in device tree node is SoC specific, so only the > > vendors know if their stmmac ethernet controller is dma coherent and > > whether their device tree are missing the critical dma-coherent property. > > What I fail to understand is how dma-coherent can make a difference in > this case. If it's not present, then the driver is supposed to maintain > caches explicitly. But it seems like explicit cache maintenance actually > causes things to break. So do we need to assume that DMA coherent > devices in generally won't work if the driver manages caches explicitly? > > I always figured dma-coherent was more of an optimization, but this > seems to indicate it isn't. There is a real failure scenario when the device is actually dma- coherent, but the DT claims it isn't: If a location from e.g. a receive buffer is already allocated in the cache, the write from the device will update the cache line and not go out to memory. If you then do the usual non-coherent cache maintenance, i.e. invalidate the RX buffer area after the device indicated the reception of the buffer, you will destroy the updated data in the cache and read stale data from memory. Regards, Lucas
