On Fri, Jan 03, 2025 at 06:04:02AM +0000, Vishwaroop A wrote: > Set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using > PLLC as the parent clock. These frequencies allow Quad IO DT > reads up to 99.99 MHz, which is the fastest that can be > achieved considering various PLL and clock divider constraints. > > Populate the DMA and IOMMU properties for the Tegra234 QSPI devices to > enable DMA support. > > Change-Id: I1dded904aa8e0f278c89998481e829f1ce474e8c > Signed-off-by: Vishwaroop A <va@xxxxxxxxxx> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index 984c85eab41a..96d0f13390ae 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -2948,6 +2948,13 @@ > <&bpmp TEGRA234_CLK_QSPI0_PM>; > clock-names = "qspi", "qspi_out"; > resets = <&bpmp TEGRA234_RESET_QSPI0>; > + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, > + <&bpmp TEGRA234_CLK_QSPI0_PM>; > + assigned-clock-rates = <199999999 99999999>; > + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; > + dma-names = "rx", "tx"; > + dma-coherent; > + iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; > status = "disabled"; > }; > > @@ -3031,6 +3038,13 @@ > <&bpmp TEGRA234_CLK_QSPI1_PM>; > clock-names = "qspi", "qspi_out"; > resets = <&bpmp TEGRA234_RESET_QSPI1>; > + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, > + <&bpmp TEGRA234_CLK_QSPI1_PM>; > + assigned-clock-rates = <199999999 99999999>; > + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; > + dma-names = "rx", "tx"; > + dma-coherent; > + iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; > status = "disabled"; > }; > It looks like these are missing the "dmas" properties that go along with "dma-names". Thierry
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