Hi Ben, On Mon, 22 Apr 2024, Ben Dooks wrote:
On 21/04/2024 11:46, Marc Dietrich wrote:The i2c controller needs to read back the data written to its registers. This way we can avoid the long delay in the interrupt handler. Signed-off-by: Marc Dietrich <marvin24@xxxxxx> --- drivers/staging/nvec/nvec.c | 41 ++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c index 45df190c2f94..214839f51048 100644 --- a/drivers/staging/nvec/nvec.c +++ b/drivers/staging/nvec/nvec.c @@ -570,6 +570,22 @@ static void nvec_tx_set(struct nvec_chip *nvec) (uint)nvec->tx->size, nvec->tx->data[1]); } +/** + * i2c_writel - safely write to an I2C client controller register + * @val: value to be written + * @reg: register to write to + * + * A write to an I2C controller register needs to be read back to make sure + * that the value has arrived. + */ +static void i2c_writel(u32 val, void *reg) +{ + writel_relaxed(val, reg); + + /* read back register to make sure that register writes completed */ + readl_relaxed(reg); +}I thought the default behaviour of writel() should be to force writes out of any CPU buffers. Are there any bus isuses here causing the code to be necessary (and if so, why is there another buffer breaking the writel behaviour?)
if fear that's a question only NVIDIA can answer. Marc
