Re: [PATCH] staging: nvec: make i2c controller register writes robust

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Hi Greg,

On Sun, 21 Apr 2024, Greg KH wrote:

On Sun, Apr 21, 2024 at 12:46:42PM +0200, Marc Dietrich wrote:
The i2c controller needs to read back the data written to its registers.
This way we can avoid the long delay in the interrupt handler.

Signed-off-by: Marc Dietrich <marvin24@xxxxxx>
---
...
+ * A write to an I2C controller register needs to be read back to make sure
+ * that the value has arrived.
+ */
+static void i2c_writel(u32 val, void *reg)
+{
+	writel_relaxed(val, reg);
+
+	/* read back register to make sure that register writes completed */
+	readl_relaxed(reg);

Do you need to compare the value to make sure it happened properly?

And how is this an i2c write?  Normally that implies this is using the
i2c core functions, this name is going to get confusing very quickly...

I just used the same name as in i2c-tegra, which may be helpful when the drivers will be merged in the future. The reason why a readback is needed is descibed in commit ec7aaca2f6. As far as I understand (it is not mentioned in the TRM AFAIK), writes are somehow buffered and a readback guaranties that the write really reached the controller. The alternative was just to wait some time...
From the commit message it seems that this only applies to the interrupt
status register, but it does not harm the do this also for the data registers just like the host driver does.

Best regards,

Marc




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