Since we have now a common helper to read port properties use it instead of sparse home grown solution. Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Reviewed-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx> Tested-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx> --- drivers/tty/serial/8250/8250_bcm7271.c | 56 +++++++++----------------- 1 file changed, 19 insertions(+), 37 deletions(-) diff --git a/drivers/tty/serial/8250/8250_bcm7271.c b/drivers/tty/serial/8250/8250_bcm7271.c index 1532fa2e8ec4..5daa38d9c64e 100644 --- a/drivers/tty/serial/8250/8250_bcm7271.c +++ b/drivers/tty/serial/8250/8250_bcm7271.c @@ -935,17 +935,14 @@ static void brcmuart_init_debugfs(struct brcmuart_priv *priv, static int brcmuart_probe(struct platform_device *pdev) { struct resource *regs; - struct device_node *np = pdev->dev.of_node; const struct of_device_id *of_id = NULL; struct uart_8250_port *new_port; struct device *dev = &pdev->dev; struct brcmuart_priv *priv; struct clk *baud_mux_clk; struct uart_8250_port up; - int irq; void __iomem *membase = NULL; resource_size_t mapbase = 0; - u32 clk_rate = 0; int ret; int x; int dma_irq; @@ -953,15 +950,12 @@ static int brcmuart_probe(struct platform_device *pdev) "uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb" }; - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv), GFP_KERNEL); if (!priv) return -ENOMEM; - of_id = of_match_node(brcmuart_dt_ids, np); + of_id = of_match_node(brcmuart_dt_ids, dev->of_node); if (!of_id || !of_id->data) priv->rate_table = brcmstb_rate_table; else @@ -1011,7 +1005,23 @@ static int brcmuart_probe(struct platform_device *pdev) } } - of_property_read_u32(np, "clock-frequency", &clk_rate); + dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not "); + + memset(&up, 0, sizeof(up)); + up.port.type = PORT_BCM7271; + up.port.dev = dev; + up.port.mapbase = mapbase; + up.port.membase = membase; + up.port.handle_irq = brcmuart_handle_irq; + up.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE; + up.port.private_data = priv; + + ret = uart_read_port_properties(&up.port); + if (ret) + goto release_dma; + + up.port.regshift = 2; + up.port.iotype = device_is_big_endian(dev) ? UPIO_MEM32BE : UPIO_MEM32; /* See if a Baud clock has been specified */ baud_mux_clk = devm_clk_get_optional_enabled(dev, "sw_baud"); @@ -1023,39 +1033,11 @@ static int brcmuart_probe(struct platform_device *pdev) priv->baud_mux_clk = baud_mux_clk; init_real_clk_rates(dev, priv); - clk_rate = priv->default_mux_rate; + up.port.uartclk = priv->default_mux_rate; } else { dev_dbg(dev, "BAUD MUX clock not specified\n"); } - if (clk_rate == 0) { - ret = dev_err_probe(dev, -EINVAL, "clock-frequency or clk not defined\n"); - goto release_dma; - } - - dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not "); - - memset(&up, 0, sizeof(up)); - up.port.type = PORT_BCM7271; - up.port.uartclk = clk_rate; - up.port.dev = dev; - up.port.mapbase = mapbase; - up.port.membase = membase; - up.port.irq = irq; - up.port.handle_irq = brcmuart_handle_irq; - up.port.regshift = 2; - up.port.iotype = of_device_is_big_endian(np) ? - UPIO_MEM32BE : UPIO_MEM32; - up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF - | UPF_FIXED_PORT | UPF_FIXED_TYPE; - up.port.dev = dev; - up.port.private_data = priv; - - /* Check for a fixed line number */ - ret = of_alias_get_id(np, "serial"); - if (ret >= 0) - up.port.line = ret; - /* setup HR timer */ hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); priv->hrt.function = brcmuart_hrtimer_func; -- 2.43.0.rc1.1.gbec44491f096