From: Thierry Reding <treding@xxxxxxxxxx>
For indented subschemas it can be difficult to understand which block an
additionalProperties property belongs to. Moving it closer to the
beginning of a block is a good way to clarify this.
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
---
.../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index c5a1ae44c5e3..1d8b99938323 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -127,6 +127,7 @@ properties:
description: The vast majority of hardware blocks of Tegra SoC belong to a
core power domain, which has a dedicated voltage rail that powers the
blocks.
+ additionalProperties: false
properties:
operating-points-v2:
description: Should contain level, voltages and opp-supported-hw
@@ -140,12 +141,11 @@ properties:
- operating-points-v2
- "#power-domain-cells"
- additionalProperties: false
-
i2c-thermtrip:
type: object
description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
exists, hardware-triggered thermal reset will be enabled.
+ additionalProperties: false
properties:
nvidia,i2c-controller-id:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -177,10 +177,9 @@ properties:
- nvidia,reg-addr
- nvidia,reg-data
- additionalProperties: false
-
powergates:
type: object
+ additionalProperties: false
description: |
This node contains a hierarchy of power domain nodes, which should match
the powergates on the Tegra SoC. Each powergate node represents a power-
@@ -225,7 +224,6 @@ properties:
"^[a-z0-9]+$":
type: object
additionalProperties: false
-
properties:
clocks:
minItems: 1
@@ -247,8 +245,6 @@ properties:
- resets
- '#power-domain-cells'
- additionalProperties: false
-
patternProperties:
"^[a-f0-9]+-[a-f0-9]+$":
type: object
--
2.41.0
