On Wed, Jul 05, 2023 at 05:30:56PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > Convert the Tegra timer bindings from the free-form text format to > json-schema. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > .../bindings/timer/nvidia,tegra20-timer.yaml | 121 ++++++++++++++++++ > .../bindings/timer/nvidia,tegra210-timer.yaml | 70 ++++++++++ > 2 files changed, 191 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml Convert? Where's the removal? > > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml > new file mode 100644 > index 000000000000..d57663d73095 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/nvidia,tegra20-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra20 (and later) Timer > + > +maintainers: > + - Thierry Reding <thierry.reding@xxxxxxxxx> > + - Jon Hunter <jonathanh@xxxxxxxxxx> > + > +description: The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free > + running counter. The first two channels may also trigger a watchdog reset. > + > + The timer found on Tegra30 provides ten 29-bit timer channels, a single 32-bit free running > + counter, and 5 watchdog modules. The first two channels may also trigger a legacy watchdog > + reset. Needs a '|' if you care about the formatting. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - nvidia,tegra114-timer > + - nvidia,tegra124-timer > + - const: nvidia,tegra30-timer > + > + - items: > + - const: nvidia,tegra30-timer > + - const: nvidia,tegra20-timer > + > + - const: nvidia,tegra20-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 4 > + maxItems: 6 > + > + clocks: > + items: > + - description: module clock > + > + clock-names: > + items: > + - const: timer > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: nvidia,tegra30-timer > + then: > + properties: > + interrupts: > + description: One interrupt per each of timer channels 1 through 5 and one shared > + interrupt for the remaining channels. > + minItems: 6 > + else: > + properties: > + interrupts: > + description: One interrupt for each timer channel. > + maxItems: 4 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +examples: > + - | > + #include <dt-bindings/clock/tegra20-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + timer@60005000 { > + compatible = "nvidia,tegra20-timer"; > + reg = <0x60005000 0x60>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&tegra_car TEGRA20_CLK_TWD>; > + }; > + > + - | > + #include <dt-bindings/clock/tegra30-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + timer@60005000 { > + compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; > + reg = <0x60005000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&tegra_car TEGRA30_CLK_TWD>; > + }; > + > + - | > + #include <dt-bindings/clock/tegra114-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + timer@60005000 { > + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; > + reg = <0x60005000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&tegra_car TEGRA114_CLK_TIMER>; > + }; > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml > new file mode 100644 > index 000000000000..2b42d8d03b7b > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/nvidia,tegra210-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra210 Timer > + > +maintainers: > + - Thierry Reding <thierry.reding@xxxxxxxxx> > + - Jon Hunter <jonathanh@xxxxxxxxxx> > + > +description: The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp > + counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock > + (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to > + generate one-shot, periodic, or watchdog interrupts. > + > +properties: > + compatible: > + const: nvidia,tegra210-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: One interrupt per each timer channels 0 through 13. > + minItems: 14 > + maxItems: 14 > + > + clocks: > + items: > + - description: module clock > + > + clock-names: > + items: > + - const: timer > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +examples: > + - | > + #include <dt-bindings/clock/tegra210-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + timer@60005000 { > + compatible = "nvidia,tegra210-timer"; > + reg = <0x60005000 0x400>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&tegra_car TEGRA210_CLK_TIMER>; > + clock-names = "timer"; > + }; > -- > 2.41.0 >
