In Tegra264 the carveouts (GSCs) used to communicate between BPMP and CPU-NS may reside in DRAM. The location will be signalled using reserved memory node in DT. Additionally some minor updates to the HSP driver are done to support the new chip. Peter De Schrijver (4): dt-bindings: mailbox: tegra: Document Tegra264 HSP dt-bindings: Add bindings to support DRAM MRQ GSCs dt-bindings: memory-region property for tegra186-bpmp firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Stefan Kristiansson (2): mailbox: tegra: add support for Tegra264 soc: tegra: fuse: add support for Tegra264 Changes in v2: - Added signoff messages - Updated bindings to support DRAM MRQ GSCs - Split out memory-region property for tegra186-bpmp - Addressed sparse errors in bpmp-tegra186.c Changes in v3: - Add #address-cells = <2> and #size-cells = <2> to nvidia,tegra264-bpmp-shmem binding example. .../firmware/nvidia,tegra186-bpmp.yaml | 37 ++- .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 + .../nvidia,tegra264-bpmp-shmem.yaml | 47 ++++ drivers/firmware/tegra/bpmp-tegra186.c | 214 ++++++++++++------ drivers/firmware/tegra/bpmp.c | 4 +- drivers/mailbox/tegra-hsp.c | 16 +- drivers/soc/tegra/fuse/tegra-apbmisc.c | 3 +- include/soc/tegra/fuse.h | 3 +- 8 files changed, 253 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml -- 2.34.1
