HI Hans, On Thu, 24 Nov 2022 09:36:14 +0100 Hans Verkuil <hverkuil-cisco@xxxxxxxxx> wrote: > Hi Luca, > > On 09/11/2022 15:18, luca.ceresoli@xxxxxxxxxxx wrote: > > From: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> > > > > Tegra20 and other Tegra SoCs have a video input (VI) peripheral that can > > receive from either MIPI CSI-2 or parallel video (called respectively "CSI" > > and "VIP" in the documentation). The kernel currently has a staging driver > > for Tegra210 CSI capture. This patch set adds support for Tegra20 VIP > > capture. > > > > Unfortunately I had no real documentation available to base this work on, > > and I started from a working downstream 3.1 kernel, that I have heavily > > reworked to fit into the existing tegra-video driver. The existing code > > appears written with the intent of being modular and allow adding new input > > mechanisms and new SoCs while keeping a unique VI core module. However its > > modularity and extensibility was not enough to add Tegra20 VIP support, so > > I added some hooks to turn hard-coded behaviour into per-SoC or per-bus > > customizable code. There are also some fixes, some generic cleanups and DT > > bindings. > > I plan on testing this series (esp. making sure it keeps working on non-tegra210 > hardware), but I have to find time for that. This is on my TODO list, so I will > get to it, but it might time. Thanks for letting me know! Indeed, with respect to what you wrote, even testing on tegra210 hardware would be useful in case you have any, as all the hardware I can access is tegra20. Kind regards. -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
