On 18/11/2022 10:08, Luca Ceresoli wrote: > description: parallel video capture interface for the VI > >>> + type: object >> >> Do you expect it to grow to more channels? > > Not on Tegra20, it has one input only, but for other SoCs it's likely. > Definitely some (including Tegra20 itself) have multiple CSI-2 inputs, > and it's reasonable that this can apply to parallel input too. > > Is this enough motivation to make room for more channels, or should I > remove it since I have no plans to introduce support for other Tegra > chips? The best would be to add some more Tegra SoCs here, so that this @0 makes sense. But I guess the block can be re-used in future, so it could also stay like this. > >>> + >>> + properties: >>> + reg: true >> >> const: 0 >> >>> + >>> + ports: >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >>> + properties: >>> + port@0: >>> + $ref: /schemas/graph.yaml#/properties/port >>> + description: >>> + Port receiving the video stream from the sensor >>> + >>> + port@1: >>> + $ref: /schemas/graph.yaml#/properties/port >>> + description: >>> + Port sending the video stream to the VI >>> + >>> + required: >>> + - port@0 >>> + - port@1 >>> + >>> + additionalProperties: false >>> + >>> + required: >>> + - reg >>> + - ports >>> + >>> +unevaluatedProperties: false >>> + >>> +required: >>> + - compatible >>> + - "#address-cells" >>> + - "#size-cells" >>> + - channel@0 >>> + >>> +# see nvidia,tegra20-vi.yaml for an example >> >> That file does not have this compatible. At least not on next-20221109. > > It's added in patch 2. It's a chicken-egg problem, should I add a third > patch that adds this line only? > > ACK for all other comments you wrote. It's ok. Best regards, Krzysztof
