On 27/10/2022 15:17, Jon Hunter wrote:
...
However, I see that I have been focused on the current issue in
front of me and this works. The alternative that I see would be to
stick with the maximum rate permitted ...
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8a33c500f93b..2099ecca4237 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -148,12 +148,14 @@ static int tegra_pwm_config(struct pwm_chip *chip,
struct pwm_device *pwm,
required_clk_rate = DIV_ROUND_UP_ULL((NSEC_PER_SEC <<
PWM_DUTY_WIDTH),
period_ns);
- err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
- if (err < 0)
- return -EINVAL;
-
- /* Store the new rate for further references */
- pc->clk_rate = clk_get_rate(pc->clk);
+ if (required_clk_rate <= clk_round_rate(pc->clk,
required_clk_rate)) {
+ err = dev_pm_opp_set_rate(pc->dev,
required_clk_rate);
+ if (err < 0)
+ return -EINVAL;
+
+ /* Store the new rate for further references */
+ pc->clk_rate = clk_get_rate(pc->clk);
+ }
}
Thinking about it some more, it is probably simpler and better to ...
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8a33c500f93b..16855f7686db 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -148,6 +148,17 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
required_clk_rate = DIV_ROUND_UP_ULL((NSEC_PER_SEC << PWM_DUTY_WIDTH),
period_ns);
+ /*
+ * If the 'required_clk_rate' is greater than the clock rate
+ * that can be provided then we will fail to configure the PWM,
+ * because the 'rate' calculation below will return 0 and which
+ * will cause this function to return -EINVAL. To avoid this, if
+ * the 'required_clk_rate' is greater than the rate returned by
+ * clk_round_rate(), set the PWM clock to the max frequency.
+ */
+ if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
+ required_clk_rate = ULONG_MAX;
+
err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
if (err < 0)
return -EINVAL;
Setting the 'required_clk_rate' to ULONG_MAX will cause the PWM to run
at the max clock. For Tegra234, this is 408MHz (assuming the PLLP is the
parent).
Jon
--
nvpublic
